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Detailed Description
Table 1-18:
Vita 57.1 FMC2 HPC Connections at J113 (Cont’d)
FPGA Pin
AC3
U20.13
J36.1
J36.3
U20.16
Net Name
FMC2_PRSNT_M2C
FMC2_TCK_BUF (1)
FMC2_TDI (1)
FMC2_TDO (1)
TMS_BUF (1)
FMC Pin
H2
D29
D30
D31
D33
Notes:
1. This signal is not directly connected to the FPGA. The value in the
leftmost column represents the device and pin the signal is
connected to. For example, U14.13 = U14 pin 13.
Table 1-19:
Power Supply Voltages for the HPC Connector
Voltage
Supply
V ADJ
3P3V AUX
3P3V
12P0V
Allowable
Voltage Range
Fixed 2.5V
3.3V
3.3V
12V
Number
of Pins
4
1
4
2
Maximum
Amps
4
0.020
3
1
Tolerance
±5%
±5%
±5%
±5%
Maximum
Capacitive Load
1,000 μF
150 μF
1,000 μF
1,000 μF
I 2 C Bus Management
[ Figure 1-2 , callout 21 ]
The I 2 C bus is controlled through U14, a four-channel I 2 C-bus multiplexer (Texas
Instruments PCA9544A). The FPGA communicates with the multiplexer through I 2 C data
and clock signals mapped to FPGA pins J24 and J23, respectively. The I 2 C idcode for the
PCA9544A device is 0x70. The bus hosts four components:
?
?
?
?
GTP transceiver power supply module
SuperClock-2 module
FMC1
FMC2
An I 2 C component can be accessed by selecting the appropriate channel through the
control register of the MUX as shown in Table 1-20 .
Table 1-20:
U27
Channel
I 2 C Channel Assignments
I 2 C Component
0
1
2
3
GTP transceiver power supply module
SuperClock-2 module
FMC1
FMC2
SP623 Board User Guide
UG751 (v1.1) September 15, 2010
www.xilinx.com
33
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